During the manufacture of integrated circuits, electrical components are formed on a semiconductor substrate through a number of process steps. For example, a typical process for forming metal oxide semiconductor ("MOS") transistors includes the steps of forming an oxide layer on a surface of a silicon substrate and a conductive gate layer on the oxide layer, masking portions of the conductive gate layer, removing unmasked portions of the conductive gate and oxide layers, and doping regions of the silicon substrate exposed by the removed portions of the gate and oxide layers. After the formation of the MOS transistors and other desired components, the resulting structure is patterned to form contact vias over portions of the components. For example, a contact via may be formed over the gate of a MOS transistor. The gate is then coupled by depositing a conductive layer in the contact via to provide interconnection among the components fabricated on the substrate.
After the conductive layer has been deposited, it is masked with a pattern of interconnections, and the unmasked portions of the conductive layer are removed by etching. The portions of the conductive layer remaining after the etch step form the interconnections of the integrated circuit. Several conventional etching techniques may be used to remove the unmasked portions of the conductive layer. Plasma etching is one such technique. The use of plasma etching in the art of semiconductor fabrication is well known, and will not be discussed in detail. A problem associated with plasma etching, in the case where the conductive layer is contacting the gate of the MOS transistor, is damage to the gate oxide resulting from an accumulation of charge on the conductive layer during the plasma etch step. If the accumulating charge creates a sufficient potential difference across the gate oxide, the oxide layer may be damaged, and permanently degrade the performance of the MOS transistor.
One solution currently employed to protect the gate oxide from charge damage is to couple the interconnect tied to the gate of the MOS transistor to a junction diode formed in the semiconductor substrate. In the case of an NMOS transistor, an n-type region is formed in a p-type substrate. The interconnect is coupled to the np-junction diode by exposing the n-type region during the formation of the contact vias, and then masking and etching the subsequently deposited conductive layer to form an interconnect that is coupled to both the gate of the MOS transistor and to the exposed n-type region. The resulting np-junction diode will provide a conductive path on which negative charge accumulated during the plasma etch step may be discharged into the semiconductor substrate. A sufficient accumulation of negative charge will forward bias the np-junction diode. However, if positive charge accumulates, the np-junction diode will be reversed biased. The positive charge will be discharged into the substrate only as a junction leakage current until the reverse breakdown voltage of the diode is exceeded. In reverse breakdown mode, the np-junction diode will act as a nearly fixed voltage source, and dissipate any accumulated positive charge.
The effectiveness of the previously described solution is reduced as the size of the semiconductor structures in an integrated circuit shrink. For example, as the size of a MOS transistor shrinks, the gate and the gate oxide are scaled accordingly. However, the breakdown voltage of the np-junction diode is not scaled as well, resulting in a relatively greater potential present across the gate oxide of the MOS transistor before the breakdown voltage of the np-junction diode is reached. Thus, the risk of the gate oxide being damaged by charge accumulation during a plasma etch step is also greater.
Therefore, there is a need for a semiconductor structure that can effectively protect the gate oxide of a MOS transistor from charging damage encountered during a plasma etch step.